One of the critical challenges for circuit designers is managing timing of their designs. Precise control over timing and clock signals can enable higher performance and increase reliability. Controlling timing, however, is becoming increasingly difficult as circuits grow more complex and clock frequencies increase.
Common clock management circuits include phase-locked loops (PLLs) and delay-locked loops (DLLs). Both PLLs and DLLs may be used to perform tasks such as de-skewing a clock signal, shifting phase of a clock signal, and synthesizing clock frequencies. A DLL generally includes at least one delay line, such as a tap-controlled delay line, for delaying signals. Clock management circuits are used in a variety of integrated circuits to manipulate clock signals. One type of integrated circuit that often includes clock management resources including PLLs and/or DLLs is a programmable logic device (PLD).
A PLD is a well-known type of integrated circuit that can be programmed to perform specified user functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., RAM, multipliers, processors, transceivers).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how all of the blocks are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FPGAs may also include various clock management circuits, each of which may include one or more PLLs and DLLs, that may be configured to manipulate clock and other timing-critical signals. For example, the Xilinx Virtex®-II FPGA includes digital clock managers (DCMs), each of which includes at least one DLL, for a variety of functions including clock de-skewing, frequency synthesis, phase shifting, and EMI reduction. (The Xilinx Virtex-II FPGA DCM is described in detail at pages 161–183 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.)
FIG. 1 shows an example clock management circuit 100 that includes a delay line. Clock management circuit 100 may be a part of an integrated circuit 190. Clock management circuit 100 may include one or more decoders 104 and 106, a delay unit 110, and a trim unit 130. An example of a clock management circuit 100 is a DCM in an FPGA, and an example of delay unit 110 is a DLL in a DCM of an FPGA. Clock management circuit 100 takes an input clock CLKIN, applies a delay based on a multi-bit DLYSEL signal, and provides the delayed clock signal as an output clock CLKOUT. The multi-bit DLYSEL signal may be an encoded signal, and may be decoded by one or more decoders 104 and 106. Delay unit 110 includes a delay line 115 and a selector 117. In particular, delay line 115 within delay unit 110 is conventionally a tap-controlled delay line (TCD) that delays a signal by a number of taps indicated by the decoded DLYSEL signal. That is, delay line 115 may include a chain of delay taps that each add a predetermined amount of delay to the input signal. By varying the length of that chain, for example by using selector circuit 117, the delay applied to the input signal may be varied. Some of the bits of the DLYSEL signal may be decoded and used to control trim unit 130. Trim unit 130 may be used to fine-tune or trim the delayed signal from delay unit 110. Typically, each trim unit step is a fractional increment of the tap delay. Thus, delay provided by clock management circuit 100 may be adjusted at in two ways. As shown in FIG. 1, bits <15:3> of DLYSEL are used to set the delay adjustment of delay unit 110, and bits <2:0> are used to set the delay adjustment of trim unit 130.
One disadvantage of a tap-controlled delay line is the delay taps in of the tap-controlled delay line may be sensitive to environmental and operating conditions such as process variations, voltage, temperature, and noise. For example, some delay lines are controlled by adjusting an analog voltage, and noise in the voltage supplies may result in fluctuations in the delay provided by each tap. This can lead to jitter in the resulting clock signals, which generally decreases the performance of the design.
Another disadvantage of tap-controlled delay lines is that they can occupy a large amount of area. Each tap, which include one or more buffers or inverters, has a fixed area, and the number of taps needed depends on the maximum delay required. For example, in a clock management circuit, the maximum delay is dictated by the lowest frequency to be supported. Thus, the design of a tap-controlled delay line requires a tradeoff between layout area and the supported frequency range. In particular, the area occupied by a delay line increases approximately linearly with increases in frequency range (which may be defined as the ratio between the maximum and minimum frequencies supported).
A further disadvantage of tap-controlled delay lines is that they may introduce duty cycle distortion. For example, differences between the rise and fall times of the delay taps used in a delay line may cause the duty cycle of an input clock signal to vary. In cases where the input signal has high frequency, duty cycle distortion of a tap-controlled delay-line may cause the clock pulse to disappear entirely. Since some of the differences in rise and fall times are introduced by the unpredictable variations in the manufacturing process, it may be impossible to avoid this effect.
Accordingly, there is a need for a circuit that addresses these and other shortcomings of conventional tap-controlled delay lines.